For many years there has been much interest in developing thin-film circuits with TFTs on glass and/or on other inexpensive insulating substrates, for large area electronics applications. Such TFTs fabricated with amorphous or polycrystalline semiconductor films may form the switching elements of a cell matrix, for example, in a flat panel display as described in U.S. Pat. No. 5,130,829 (Our Ref: PHB 33646). A more recent development involves the fabrication and integration of circuits from TFTs (often using polycrystalline silicon) as, for example, integrated drive circuits for such a cell matrix. Thus, for example, published European Patent Application EP-A-0 629 003 (Our Ref: PHB 33845) describes such an electronic device comprising on a substrate a switching matrix of thin-film switching transistors and a peripheral drive circuit located outside the matrix and comprising thin-film circuit transistors which are coupled to the switching TFTs of the matrix. The whole contents of U.S. Pat. No. 5,130,829 and EP-A-0 629 003 are hereby incorporated herein as reference material.
Unfortunately, undesirable field-induced effects occur in the transistor characteristics of such TFTs, especially those fabricated with polycrystalline silicon formed using low temperature processes. Several instability mechanisms occur, for example, on-current loss, bias-induced state creation in the polycrystalline silicon, and hot carrier induced state creation and carrier trapping. Another effect which occurs is a drain field-enhanced increase in leakage current. The degradation of the transistor characteristics (for example, off-state leakage current, threshold voltage and on-state current) can seriously limit the use of such TFTs in such circuits.
One way of reducing such effects in TFTs is by means of a field-relief region having a lower doping concentration than the drain region. The TFT comprises an insulated gate adjacent to a crystalline semiconductor film for controlling a conduction channel in the semiconductor film between source and drain regions. The field relief region is present between the conduction channel and drain region of the TFT. It may be located to the side of the gate, or it may be fully or partly overlapped by the gate.
The problem with conventional field-relief architectures is that they require an additional low-dose implantation step. A high-dose implant is needed for the formation of the source and drain, whilst a low-dose implant is required for the field-relief region. Although the introduction of a field-relief region improves TFT performance considerably, the additional implantation step complicates the TFT production process. It is desirable to fabricate the source, drain and the field-relief region in a single implantation step in order to simplify the TFT manufacturing process, which will reduce production costs and improve throughput and yield. This problem is addressed in Japanese Patent Specification No. 9148266 which describes a method of TFT fabrication wherein the edges of the gate electrode are oxidised to form porous films. The porous films are used as a mask to reduce the amount of impurity ions implanted into the active layer and thereby form field relief regions adjacent the source and drain.
It is an aim of the present invention to provide an improved method of defining field relief regions in a single implantation step.
The present invention provides a method of manufacturing an electronic device including a thin film transistor, comprising the steps of:
(a) forming a semiconductor film over an insulating substrate;
(b) depositing a first masking layer over the semiconductor film and removing portions thereof to form a plurality of holes therethrough which extend substantially perpendicularly from the upper to the lower surface thereof;
(c) patterning the first masking layer in a first pattern;
(d) depositing a second masking layer over the first masking layer;
(e) patterning the second masking layer to define a second pattern that lies within the area of the first pattern; and
(f) implanting the semiconductor film, using at least the first masking layer as an implantation mask, with a portion of the first masking layer which defines at least some of the holes partially masking the implantation, such that the implantation defines source and drain regions, an undoped conduction channel between the source and drain regions, and a field-relief region having a lower doping concentration than the drain region between the conduction channel and the drain region.
Combined implantation of source, drain and field-relief regions can thus be achieved with the use of a masking layer or template for the definition of the field-relief region, which reduces the implant dose in a controlled fashion relative to the source and drain regions where there is no template.
The first masking layer defines a large number of vertical holes that reach down to the layer beneath, through which the dopant is implanted. The fraction of the template area that is covered with holes determines the effective dopant concentration in the region defined by the template. An increase in the number of holes and a reduction in the hole size will produce a quasi-homogeneous doping profile in the field-relief region, whose doping uniformity can be improved further in a subsequent combined dopant activation and diffusion process using a laser to diffuse the dopant laterally in the molten silicon. The doping dose and distribution can therefore be readily dictated in a controllable manner by selecting a suitable density and size of holes. Techniques which facilitate this are discussed below.
With the approach disclosed in the Japanese Patent Specification No. 9148266 referred to above, the dopant concentration in the field relief regions may only be adjusted relative to the dopant concentration in the source and drain regions by varying the thickness of the oxide layer.
Depending on their number and size, the holes in the template may be prepared using for example lithography or “nanotechnology”, that is techniques for defining features having dimensions of the order of nanometers rather than micrometers.
Step (b), that is the formation of a first masking layer over the semiconductor film having a plurality of holes therethrough may comprise providing an array of spaced raised features over the semiconductor film, depositing the first masking layer thereover, and removing the raised features together with the portions of the first masking layer material overlying the raised features. Alternatively, step (b) may comprise depositing a first masking layer over the semiconductor film, defining an etchant mask over the first masking layer, and etching a plurality of holes through the material of the first masking layer.
Step (c), patterning the first masking layer in a first pattern, may be carried out before the step of etching holes in the first masking layer.
In a preferred embodiment of the method, the step of forming holes in the first masking layer is carried out after step (e), such that the holes are formed through the exposed areas of the first masking layer.
The patterning of the first and second masking layers may be achieved in several ways. In a preferred process, step (d) is carried out before step (c), and the method includes a further step (h) after step (d) and before step (c) of patterning the second masking layer to form a mask in the first pattern for the patterning of the first masking layer in step (c). More particularly, wherein step (h) may comprise defining the second pattern in the second masking layer and then forming sidewall spacers adjacent the second masking layer to define the first pattern.
The step (e) of patterning the second layer may comprise defining the second pattern in a third masking layer over the second masking layer, oxidising the exposed portions of the second masking layer, and then removing the oxidised portions of the second masking layer thereby defining the second pattern in the second masking layer.
The use of this oxidation technique or spacers enables the formation of relatively narrow field relief regions, reducing the associated parasitic capacitance and series resistance.
Preferably, the first masking layer may form a gate electrode layer, and the method includes a step of depositing a gate insulator layer after step (a) and before step (b). This enables the formation of fully self-aligned, gate-overlapped lightly-doped-drain (FSA GOLDD) device structures.
Alternatively, the first masking layer forms a gate insulating layer and the second masking layer forms a gate electrode layer.
According to another aspect, the present invention provides an electronic device including a thin film transistor which comprises a patterned semiconductor film on an insulating substrate, a gate insulator layer over the semiconductor film, and a gate electrode over the gate insulator layer, the semiconductor film comprising source and drain regions, an undoped conduction channel between the source and drain regions, and a field-relief region having a lower doping concentration than the drain region between the conduction channel and the drain region, wherein a portion of the gate electrode overlaps the field-relief region and has a plurality of holes defined therethrough which extend substantially perpendicularly from the upper to the lower surface thereof.
In accordance with a further aspect, the present invention provides an electronic device including a thin film transistor which comprises a patterned semiconductor film on an insulating substrate, a gate insulator layer over the semiconductor film, and a gate electrode over the gate insulator layer, the semiconductor film comprising source and drain regions, an undoped conduction channel between the source and drain regions, and a field-relief region having a lower doping concentration than the drain region between the conduction channel and the drain region, wherein a portion of the gate insulator layer overlaps the field-relief region and has a plurality of holes defined therethrough which extend substantially perpendicularly from the upper to the lower surface thereof, and the gate electrode is self-aligned with the conduction channel.
Preferably, the length of the field-relief region is less than 1 μm. The use of, for instance, a spacer technology, oxidation of a patterned mask layer or overetching of a patterned mask layer allow the formation of a relatively narrow field relief region, with a length which may be well below 1 μm.
The holes in the first masking layer may expose around 1 to 10% of the underlying layer with a view to optimising the stability of the TFT. The average hole diameter is preferably less than 100 nm.
The layer definition and implantation methods used to fabricate the TFTs may adopt known technologies and process steps, which will be apparent to those skilled in the art. The source and drain regions and field-relief regions may be doped regions of the one conductivity type present in the semiconductor film, and/or they may be doped regions of one or more additional semiconductor films adjacent to the said semiconductor film. Gate-aligned processes may be used in order to reduce parasitic effects. Thus, for example, at least some of the circuit TFTs may have their field relief region substantially entirely overlapping with the gate, and the gate of these TFTs and/or of other circuit TFTs may have an edge which is substantially aligned with an edge of the drain region.
It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the Drawings.